The following valid line of VHDL code:
constant MY_CONSTANT : integer := 2 ** 16;
Appears as an error in vhdl-tool:
message: 'No matches for binary operator "**" with left argument type "Universal integer" and right argument type "Universal integer"'
Similarly, I also get an error for this line:
empty <= not pipe_valid(FIFO_DEPTH);
message: 'Expected signal assignment: empty'
Fixed in master. Will be in the next release.