#8 Signal used as array index is "declared but not read"

Version 0.0.2
Hash: 947bf11409c635d9d7930207b0f1bf88b6c3e230
Date: Tue Aug 1 23:26:03 2017 +1000

library ieee;
use ieee.std_logic_1164.all;

entity unused_signal is
    port(
        iClk            : in  std_logic;
        oSelect_me      : out std_logic_vector(0 to 100)
   );
end unused_signal;

architecture rtl of unused_signal is
    -- index is "declared but not read"
    signal index : natural range 0 to 100;
begin
    index <= 10;

    process (iClk)
    begin
        if rising_edge(iClk) then
            -- index is read below
            oSelect_me          <= (others => '0');
            oSelect_me(index)   <= '1';
        end if;
    end process;
end architecture rtl;

I have a signal that is read in a clocked process as an array index. VHDL-Tool reports that the signal is declared but not read. Using VHDL-Tool version: Version 0.0.2 Hash: 947bf11409c635d9d7930207b0f1bf88b6c3e230 Date: Tue Aug 1 23:26:03 2017 +1000 Code example: library ieee; use ieee.std_logic_1164.all; entity unused_signal is port( iClk : in std_logic; oSelect_me : out std_logic_vector(0 to 100) ); end unused_signal; architecture rtl of unused_signal is -- index is "declared but not read" signal index : natural range 0 to 100; begin index <= 10; process (iClk) begin if rising_edge(iClk) then -- index is read below oSelect_me <= (others => '0'); oSelect_me(index) <= '1'; end if; end process; end architecture rtl;

Fixed. Will be in 0.0.4 release.