"Missing from sensitivity list" warning does not check "if" statements

See example code below. The attached code has no warnings from VHDL-tool, despite missing sensitivities in the second process. It appears as if sensitivities are not checked when signals are read from an if statement.

Using VHDL-tool 0.0.2 (I think, it reports 0.0.1):

Hash: 637058790087f04dab3f35dcea4bab03470eec36
Date: Wed Jul 12 21:46:11 2017 +1000

Example code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity same_number_checker is
    port (
        iClk                            : in    std_logic;

        iNumber                         : in    unsigned(31 downto 0);
        oSame_1                         : out   std_logic;
        oSame_2                         : out   std_logic
    );
end same_number_checker;

architecture rtl of same_number_checker is
    signal number_d1 : unsigned(31 downto 0);
begin

    -- Needs iNumber and number_d1 in sensitivity list to avoid warnings
    process (iNumber, number_d1)
    begin
        oSame_1 <= '1' when iNumber = number_d1 else '0';
    end process;

    -- No warnings from this block, even though it reads iNumber and number_d1
    process ()
    begin
        oSame_2 <= '0';
        if iNumber = number_d1 then
            oSame_2 <= '1';
        end if;
    end process;

    process (iClk)
    begin
        if rising_edge(iClk) then
            number_d1 <= iNumber;
        end if;
    end process;

end rtl;

#7 "Missing from sensitivity list" warning does not check "if" statements