#50 VHDL 2008 implicit boolean type error

  signal a : std_logic;
  signal x : std_logic;
  signal y : std_logic;

begin

  x <= '1' when a else '0';

  process (a)
  begin
    if a then
      y <= '1';
    end if;
  end process;

Hi, I am getting a type error when using the 2008 language feature that allows a std_logic type to be used in a conditional (if, when, etc.) as if it were a boolean if the value the input should equal is not specified. For example: signal a : std_logic; signal x : std_logic; signal y : std_logic; begin x <= '1' when a else '0'; process (a) begin if a then y <= '1'; end if; end process; This would be an error if not using VHDL 2008, but should be valid VHDL 2008 code. Thanks