#30 false error with simulation code

process(clk)

file outfile : text is out "/data/output.txt";   -- <-- This gives error

... begin ... end process;

The line above gives an error with description: "Error parsing prefix operator thing" This code is valid for simulation.

That's an old VHDL-87 style file declaration, which vhdl-tool didn't previously support. We've updated the parser so that it is now supported in version 0.0.8, which is available from the downloads page.