Hey, do you have any plans to add VHDL 2008 support?
Probably the hardest part about adding VHDL 2008 support is finding VHDL 2008 source code to test with. If you have any examples, that would make things much easier.
Which features do you need?
We are using things like:
So yeah, quite a lot when I look at it now... 8-/
Yeah, its a reasonable amount of work. Those features will probably take a couple of months to implement.
A specific example of the unconstrained types we use that would be nice to support:
type std_logic_vector_array is array (natural range <>) of std_logic_vector;
signal some_numbers : std_logic_vector_array(GENERIC_ARRAY_SIZE-1 downto 0)(GENERIC_VECTOR_SIZE-1 downto 0) := (others => (others => '-'));
signal a_number : some_numbers'subtype; -- Equivalent to std_logic_vector(GENERIC_VECTOR_SIZE-1 downto 0)
More 2008 stuff...
I am trying to add the std libraries for 2008 provided with vivado, typically found in:
It has some wacky unicode stuff in from line 40 that vhdl-tool doesn't like. The std libraries packaged with questasim have the same problem.
Not sure if this one is 2008 or not, but I am using the 2008 libraries from vivado:
Basically its not picking up the to_bit function from the library for some reason:
signal value_bit : bit;
signal value_logic : std_logic;
value_bit <= to_bit(value_logic);
Edit: I think I figured this out, to_bit has a second argument that is defaulted to '0'. I have seen the same issue in some of our self-defined functions with default arguments.
No need to include the std.standard package. It is built into vhdl-tool. This is missing from the docs on the website, which I'll update.
The default arguments bug will be fixed soon. Hayden has reported it here: https://git.vhdltool.com/vhdl-tool/vhdl-tool/issues/10.
Ah, OK. But it looks like you still need to import the other std packages.
std.textio works fine.
std.env does not. We use it for the 'finish' function to end VHDL simulations. The vivado version has the following function:
function RESOLUTION_LIMIT return DELAY_LENGTH;
Where DELAY_LENGTH is defined in std.standard. Is there a way to use a different std.standard, or add this definition to the built in one?
These VHDL-2008 features have been implemneted and will be in the 0.5 release.
Could you please add support for VHDL-2008 contexts? I use VUnit, which makes heavy use of contexts. Ideally, I would be able to use VHDL-Tool with the entirety of VUnit. I believe they use some other features of VHDL-2008 too.
Here are some other VHDL-2008 features I think would be really useful:
Edit: Apparently I can't read well.