#12 VHDL 2008 support

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opened 2 years ago by andymcc · 10 comments
andymcc commented 2 years ago

Hey, do you have any plans to add VHDL 2008 support?

Hey, do you have any plans to add VHDL 2008 support?
vhdl-tool commented 2 years ago
Owner

Yep.

Probably the hardest part about adding VHDL 2008 support is finding VHDL 2008 source code to test with. If you have any examples, that would make things much easier.

Which features do you need?

Yep. Probably the hardest part about adding VHDL 2008 support is finding VHDL 2008 source code to test with. If you have any examples, that would make things much easier. Which features do you need?
andymcc commented 2 years ago
Poster

We are using things like:

  • generate elsif /else
  • (all) sensitivity list
  • Implicit use of ?? to convert std_logic to booleans in if statements
  • Unconstrained types (arrays of std_logic_vector)
  • Matching case (case?)
  • reduction operators
  • matching relational operators
  • expressions in port maps
  • reading output ports

So yeah, quite a lot when I look at it now... 8-/

We are using things like: * generate elsif /else * (all) sensitivity list * Implicit use of ?? to convert std_logic to booleans in if statements * Unconstrained types (arrays of std_logic_vector) * Matching case (case?) * reduction operators * matching relational operators * expressions in port maps * reading output ports So yeah, quite a lot when I look at it now... 8-/
vhdl-tool commented 2 years ago
Owner

Yeah, its a reasonable amount of work. Those features will probably take a couple of months to implement.

Yeah, its a reasonable amount of work. Those features will probably take a couple of months to implement.
andymcc commented 2 years ago
Poster

A specific example of the unconstrained types we use that would be nice to support:

type std_logic_vector_array is array (natural range <>) of std_logic_vector;
signal some_numbers : std_logic_vector_array(GENERIC_ARRAY_SIZE-1 downto 0)(GENERIC_VECTOR_SIZE-1 downto 0) := (others => (others => '-'));
signal a_number : some_numbers'subtype; -- Equivalent to std_logic_vector(GENERIC_VECTOR_SIZE-1 downto 0)
A specific example of the unconstrained types we use that would be nice to support: ```vhdl type std_logic_vector_array is array (natural range <>) of std_logic_vector; signal some_numbers : std_logic_vector_array(GENERIC_ARRAY_SIZE-1 downto 0)(GENERIC_VECTOR_SIZE-1 downto 0) := (others => (others => '-')); signal a_number : some_numbers'subtype; -- Equivalent to std_logic_vector(GENERIC_VECTOR_SIZE-1 downto 0) ```
andymcc commented 2 years ago
Poster

More 2008 stuff...

I am trying to add the std libraries for 2008 provided with vivado, typically found in: //Xilinx/Vivado/2017.3/data/vhdl/src/std_2008/*.vhd

It has some wacky unicode stuff in from line 40 that vhdl-tool doesn't like. The std libraries packaged with questasim have the same problem.

More 2008 stuff... I am trying to add the std libraries for 2008 provided with vivado, typically found in: /<your_install_path>/Xilinx/Vivado/2017.3/data/vhdl/src/std_2008/*.vhd It has some wacky unicode stuff in from line 40 that vhdl-tool doesn't like. The std libraries packaged with questasim have the same problem.
andymcc commented 2 years ago
Poster

Not sure if this one is 2008 or not, but I am using the 2008 libraries from vivado: //Xilinx/Vivado/2017.3/data/vhdl/src/ieee_2008/*.vhd

Basically its not picking up the to_bit function from the library for some reason:

architecture ...
    signal value_bit : bit;
    signal value_logic : std_logic;
begin
    value_bit <= to_bit(value_logic);

Edit: I think I figured this out, to_bit has a second argument that is defaulted to '0'. I have seen the same issue in some of our self-defined functions with default arguments.

Not sure if this one is 2008 or not, but I am using the 2008 libraries from vivado: //Xilinx/Vivado/2017.3/data/vhdl/src/ieee_2008/*.vhd Basically its not picking up the to_bit function from the library for some reason: ```vhdl architecture ... signal value_bit : bit; signal value_logic : std_logic; begin value_bit <= to_bit(value_logic); ``` Edit: I think I figured this out, to_bit has a second argument that is defaulted to '0'. I have seen the same issue in some of our self-defined functions with default arguments.
vhdl-tool commented 2 years ago
Owner

No need to include the std.standard package. It is built into vhdl-tool. This is missing from the docs on the website, which I'll update.

The default arguments bug will be fixed soon. Hayden has reported it here: https://git.vhdltool.com/vhdl-tool/vhdl-tool/issues/10.

No need to include the std.standard package. It is built into vhdl-tool. This is missing from the docs on the website, which I'll update. The default arguments bug will be fixed soon. Hayden has reported it here: https://git.vhdltool.com/vhdl-tool/vhdl-tool/issues/10.
andymcc commented 1 year ago
Poster

Ah, OK. But it looks like you still need to import the other std packages.

std.textio works fine. std.env does not. We use it for the 'finish' function to end VHDL simulations. The vivado version has the following function:

function RESOLUTION_LIMIT return DELAY_LENGTH;

Where DELAY_LENGTH is defined in std.standard. Is there a way to use a different std.standard, or add this definition to the built in one?

Ah, OK. But it looks like you still need to import the other std packages. std.textio works fine. std.env does not. We use it for the 'finish' function to end VHDL simulations. The vivado version has the following function: ```vhdl function RESOLUTION_LIMIT return DELAY_LENGTH; ``` Where DELAY_LENGTH is defined in std.standard. Is there a way to use a different std.standard, or add this definition to the built in one?
vhdl-tool commented 1 year ago
Owner

These VHDL-2008 features have been implemneted and will be in the 0.5 release.

These VHDL-2008 features have been implemneted and will be in the 0.5 release.

Hi,

Could you please add support for VHDL-2008 contexts? I use VUnit, which makes heavy use of contexts. Ideally, I would be able to use VHDL-Tool with the entirety of VUnit. I believe they use some other features of VHDL-2008 too.

Here are some other VHDL-2008 features I think would be really useful:

  • Conditional assignment and selected signal assignment in processes
  • Enhanced bit string literals
  • Slices in aggregates
  • External (hierarchical) names
  • Force/release
  • Type generics
  • Package generics

Edit: Apparently I can't read well.

Hi, Could you please add support for VHDL-2008 contexts? I use [VUnit](https://github.com/VUnit/vunit), which makes heavy use of contexts. Ideally, I would be able to use VHDL-Tool with the entirety of VUnit. I believe they use some other features of VHDL-2008 too. Here are some other VHDL-2008 features I think would be really useful: - ~~Conditional assignment and selected signal assignment in processes~~ - ~~Enhanced bit string literals~~ - Slices in aggregates - External (hierarchical) names - Force/release - ~~Type generics~~ - ~~Package generics~~ Edit: Apparently I can't read well.
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