#11 Inferred latch and not in sensitivity list warning in clocked process if signal anded with rising_edge()

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opened 8 years ago by mikechong · 1 comments

The following snippet gives an inferred latch and "en" not in sensitivity list warning:

process(iCLK)
begin  
    if rising_edge(iCLK) and en = '1' then
        d <= q;
    end if;
end process;

It should be equivalent to the following, which lints fine:

process(iCLK)
begin  
    if rising_edge(iCLK) then
        if en = '1' then
            d <= q;
        end if;
    end if;
end process;
The following snippet gives an inferred latch and "en" not in sensitivity list warning: process(iCLK) begin if rising_edge(iCLK) and en = '1' then d <= q; end if; end process; It should be equivalent to the following, which lints fine: process(iCLK) begin if rising_edge(iCLK) then if en = '1' then d <= q; end if; end if; end process;
vhdl-tool commented 8 years ago
Owner

Will be fixed in the 0.4 release.

Will be fixed in the 0.4 release.
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