alexsh3

alexsh3 opened issue vhdl-tool/vhdl-tool#58

Problem parsing VUnit

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#57

Labels on end if not supported

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#56

Types used in packages not checked

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#55

Does not check for missing ports in an entity instantiation

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#54

Declaration and constraint of unconstrained record types not checked

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#53

Goto definition on entity name goes to architecture

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#52

No matches for function endfile

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#51

Syntax for signal declaration using 'subtype with an initial value

2 months ago

alexsh3 opened issue vhdl-tool/vhdl-tool#50

VHDL 2008 implicit boolean type error

2 months ago